HDL Designer 2008.1

HDL Designer delivers solutions optimizing the design creation, synthesis and verification processes of advanced ASIC and FPGA designs in a team environment.

Comprehensive Design Creation & RTL Reuse Environment

• Any Silicon
  PLD, FPGA, Platform FPGA, Structured ASIC, ASIC Prototypes, ASICs and SOCs
• Any Vendor
  Actel, Altera, Atmel, ChipExpress, Lattice, Xilinx, plus any ASIC foundry
• Any Language
  VHDL, Verilog, SystemVerilog, C/C++, PSL
• Any Flow
  Integrated with all leading Simulation, Emulation & Formal solutions
  Integrated with all commercial synthesis and P & R environments

Optimizing RTL Reuse

• Practical reuse (online demo) (datasheet)

Optimizing The Design Process

• Cut design time in half: Rapid design development process
• Team productivity: Team design flow and version management
• Tune your competitive edge: Flow management and customization
• Cut lab time: FPGA centric analysis and debug
• Optimize system timing closure: I/O optimization & PCB integration
• Integrate verification: Advanced Debug

Design Solutions

• RTL Reuse and Code Quality Assessment with Scoring
• Multi-lingual Text Design Tools
• Advanced State Machine Design
• Hybrid Text Based Design
• HDL Centric Block Based Design
• Team Design & Data Management

product:Mentor Graphics HDL Designer Series 2008.1
Lanaguage:english
Platform:Winxp/Win7
Size:237MB